职责范围: 1. Develop SRAM/ROM compilers and customized macros. 2. Develop SRAM/ROM
characterization flow and deliver design kits. 3. Develop Memory compiler tiling
code. 职位要求: 1. Candidate must have a MS degree or above in Electrical or Computer
Engineering 2. Knowledge on transistor level circuit design and layout design. 3. Experience
in spice simulation or fast spice simulation. 4. Familiarity with Verilog and Synopsys
.lib. 5. Ability in scripting language, such as Perl/Python/shell/tcl
立即申请
数字电路设计工程师-上海查看详情收起详情
公司/部门: 台积电(中国)
学历要求: 硕士
招聘人数: 若干
岗位介绍:
职责范围: 1. Develop advanced standard cell and GPIO libraries on advanced process technologies (6nm,
7nm, 12/16nm, 22/28nm, etc.) 2. Take challenging tasks from circuit design to SOC design to achieve
world-class PPA performance (high-performance, low-power, and area-effective) 职位要求: 1. Good
knowledge of circuits design. Experience in digital circuit or analog design is preferred. 2.
Experience in Cadence/Synopsys/Mentor EDA tools and Linux/Unix environment is preferred 3. CAD and
script capability such
立即申请
芯片前端设计工程师-上海查看详情收起详情
公司/部门: 台积电(中国)
学历要求: 硕士
招聘人数: 若干
岗位介绍:
职责范围: 1. RTL synthesis, SDC/UPF verification, low power design implementation for advanced
technology chips. 2. Design flow/methodology development and innovation for front-end design
challenges. 3. Be responsible for RTL verification, synthesis, low power design, and STA/timing
closure works for customer’s projects and internal system test chips .职位要求: 1. MS or above in
EE, CS related fields. Experience in Digital IC design flow (from Synthesis, DFT, MBIST, Formality,
STA), RTL design, RTL verificat
立即申请
Layout Engineer(IP版图设计工程师)-上海查看详情收起详情
公司/部门: 台积电(中国)
学历要求: 本科
招聘人数: 若干
岗位介绍:
职责范围: 1.Full layout design for standard cell/IO/SRAM IPs in advanced process nodes 2.Work on
the physical verification (DRC/LVS/Antenna ...) 3.Work on test chip layout design and
verification 4.Close cooperation with designers on PPA optimization 职位要求: 1.At least BS
Degree of Microelectronics or Physics. 2.Excellent graduate or at least 1 years related working
experience 3.Familiar with layout design and verification tools (Virtuoso, Laker,
Calibre) 4.Familiar with design rule and layout effect in advanced process. 5.Excellent skills
of communication and teamwork are also expected. 6.Programming experience (Perl/tcl skill) will be
a plus. 7.Experience in advanced process (n16 and beyond) will be a plus. 立即申请
DRC/LVS开发工程师-上海查看详情收起详情
公司/部门: 台积电(中国)
学历要求: 硕士
招聘人数: 若干
岗位介绍:
职责范围: 1.Work closely with process RD team to develop DRC/LVS for design readiness. 2.Provide
customer support to world-wide leading design house. 3.Initial more innovation to continue optimize
development efficiency. 4.Work closely with various departments (Physical design/integration/Device
RD/Product/ESD) on their design requirements. 5.Work closely with EDA partner for tool
qualification and methodology enhance. 职位要求: 1.Good knowledge of semiconductor FEOL/BEOL
process and chip design concepts. Solid understanding of device physics, Layout design is a
plus. 2.Knowledge of EDA partner (Mentor, Synopsys, Cadence, etc.) tools suite is a plus.
Especially Laker /Virtuoso /Calibre. 3.Scripting and programming experience using several of the
following: Perl, Python, C, C++, TCL, Skill. 4.Ability to work across teams to drive a solution,
problem solver and self-motivated. 5.The ideal candidate will have experience in DRC/LVS
development. 6.MS or above in EE, CS related fields. 立即申请
SPICE Modeling Engineer(器件模型工程师)-上海查看详情收起详情
公司/部门: 台积电(中国)
学历要求: 硕士
招聘人数: 若干
岗位介绍:
岗位职责: 1.Testkey design for SPICE modeling 2.SPICE model release for advanced and mainstream
process 3.Device characterization 4.Customer support 5.Automation development on all
SPICE modeling flow 任职资格: 1.Minimum MS degree majoring in EE, Physics or Engineering related
fields. 2.Related experience in semiconductor device, measurement, extraction and SPICE
simulation. 3.Proficiency in programming language, such as Perl or Python or C++ or VB.Net.4.Must
be effectively bilingual in Mandarin and English.
立即申请
职责范围:
1.负责薄膜、黄光、蚀刻 、
离子扩散、机械研磨等设备机台的维护及效能精进。 2.处理高科技设备故障。 3.提高设备效率。 4.计划和执行分析或缺陷检测项目。 5.与跨职能工程师或供应商沟通。 1.
Handle Diffusion, Thin Film, Lithography or Etching equipment. 2. Warm up and trouble solve with
high tech. equipment. 3. Improve and enhance the efficiency of equipment. 4. Plan and execute
the analysis or defect detection projects. 5. Communicate with cross function engineers or
vendors.
职位要求:
1.本科及以上学历。电子、电气、机械及自动化相关专业。 2.无需经验(有设备维护或改进经验者优先)。 3.具备基本的机械相关知识。有半导体工艺知识者优先。 4.良好的解决问题能力,沟通能力,团队精神,积极的学习态度,英语能力强。 1.
Bachelor degree and above. Major in Electronics, Electrical Engineering, Mechanical and Automation
Engineering related fields. 2. No experience required (having experience with equipment maintenance
or improvement is a plus). 3. Have basic mechanical related knowledge. Having the semiconductor
processes knowledge is a plus. 4. Good problem solving skills, communication ability, team spirit,
active learning attitude and is adequate in English. 立即申请
职责范围: 1.在线问题处理:解决在线制程问题,确保流程的顺畅,协助新制程导入与技术转移,解决工艺异常及减少工艺缺陷,产品良率。 2.计划并执行改进制程良率与降低制造成本的项目,提升及改善工艺能力。 3.与器件,整合,良率提升,制程整合,制造部等多部门跨部门合作。 1.
Advanced module process development and baseline sustaining. 2. Process
stability/manufacturability improvement for yield and reliability qualification. 3.
Working with a team which may include device, integration, yield, module, manufacturing
and external suppliers to drive leading-edge integrated module development, control and
improvements.
任职资格: 1.良好的解决问题能力,沟通能力,团队精神,积极的学习态度,英语能力强。 2.具有良好的开放式沟通能力,能够在跨职能团队中工作,包括内部和外部合作伙伴。 3.英语流利。 4.较强的统计过程控制(SPC)和/或实验设计(DOE)原理知识。 5.需要基于基础而非经验模型的强大的技术问题解决和分析能力。 6.动手参与和强烈的主人翁精神。 7.可以适应Fab内的工作环境,接受小夜班。 1.
Minimum Master degrees in Bachelor Science, Electrical Engineering, Chemical Engineering, Mechanical
Engineering, Physics, Chemistry or a related engineer discipline. 2. Exhibit good and open
communication skills, be able to work within cross-functional teams, including internal and external
partners. 3. Fluent in English. 4. Strong knowledge of Statistical Process Control (SPC)
and/or Design of Experiments (DOE) principles. 5. Strong technical problem-solving and analytical
skills, based upon fundamental, rather than empirical models is required. 6. Hands-on participation
and a strong sense of ownership. 7. Willingness to make frequent fab presence. 立即申请
芯片前端设计工程师-南京查看详情收起详情
公司/部门: 台积电(南京)
学历要求: 硕士
招聘人数: 若干
岗位介绍:
职责范围: 1. RTL synthesis, SDC/UPF verification, low power design implementation for advanced
technology chips. 2. Design flow/methodology development and innovation for front-end design
challenges. 3. Be responsible for RTL verification, synthesis, low power design, and STA/timing
closure works for customer’s projects and internal system test chips. 职位要求: 1. MS or above in
EE, CS related fields. Experience in Digital IC design flow (from Synthesis, DFT, MBIST, Formality,
STA), RTL design, RTL verific
立即申请
芯片物理设计工程师-南京查看详情收起详情
公司/部门: 台积电(南京)
学历要求: 硕士
招聘人数: 若干
岗位介绍:
职责范围: 1. Physical implementation of advanced technology chips. 2. Design methodology
development and innovation for advanced technology challenges. 3. Be responsible for
22/16/12/10/7/5nm chip implementation for customer’s projects or internal system test chips. 4. Be
responsible for advanced node PPA benchmark, and solution development. 5. EDA tool new features
enablement. 6. Customer onsite/offsite supports will be required on demand. 职位要求: 1. MS
or above in EE, CS related fields. Experience in APR,
立即申请
芯片计算机辅助设计暨设计方法论工程师-南京查看详情收起详情
公司/部门: 台积电(南京)
学历要求: 硕士
招聘人数: 若干
岗位介绍:
职责范围: 1. Develop chip implementation infrastructure, include but not limited to general design flow
automation, design collateral/environment/data management, computing resource
allocation/analysis/monitoring, and design diagnosis solutions development. 2. Develop chip
implementation methodology algorithms to improve productivity and design PPA by machine learning and/or
expert system programming. 3. Develop chip implementation environment regression automation and
code review system to improve sou
立即申请
静态随机存储器设计工程师-南京查看详情收起详情
公司/部门: 台积电(南京)
学历要求: 硕士
招聘人数: 若干
岗位介绍:
职责范围: 1. Develop SRAM/ROM compilers and customized macros. 2. Develop SRAM/ROM
characterization flow and deliver design kits. 3. Develop Memory compiler tiling
code. 职位要求: 1. Candidate must have a MS degree or above in Electrical or Computer
Engineering 2. Knowledge on transistor level circuit design and layout design. 3. Experience
in spice simulation or fast spice simulation. 4. Familiarity with Verilog and Synopsys
.lib. 5. Ability in scripting language, such as Perl/Python/shell/tcl
立即申请
数字电路设计工程师-南京查看详情收起详情
公司/部门: 台积电(南京)
学历要求: 硕士
招聘人数: 若干
岗位介绍:
职责范围: 1. Develop advanced standard cell and GPIO libraries on advanced process technologies (6nm,
7nm, 12/16nm, 22/28nm, etc.) 2. Take challenging tasks from circuit design to SOC design to achieve
world-class PPA performance (high-performance, low-power, and area-effective) 职位要求: 1. Good
knowledge of circuits design. Experience in digital circuit or analog design is preferred. 2.
Experience in Cadence/Synopsys/Mentor EDA tools and Linux/Unix environment is preferred 3. CAD and
script capability such
立即申请
职责范围: 1. Responsible for checking the advanced chip function before fabrication. Given the
verification, the chip can exhibit expecting high performance after fabrication. 2. Reliable flow
setting, identify violation root cause, and provide the fixing strategy to achieve high quality
chips. 3. Professional at one domain of blow knowledge at least. Signoff team not only executes the
advanced signoff skill, but also push the boundary of flow to reach higher quality and productivity. a.
STA (static t
立即申请
Layout Engineer(IP版图设计工程师)-南京查看详情收起详情
公司/部门: 台积电(南京)
学历要求: 本科
招聘人数: 若干
岗位介绍:
职责范围: 1.Full layout design for standard cell/IO/SRAM IPs in advanced process nodes 2.Work on
the physical verification (DRC/LVS/Antenna ...) 3.Work on test chip layout design and
verification 4.Close cooperation with designers on PPA optimization 职位要求: 1.At least BS
Degree of Microelectronics or Physics. 2.Excellent graduate or at least 1 years related working
experience 3.Familiar with layout design and verification tools (Virtuoso, Laker,
Calibre) 4.Familiar with design rule and layout effect in advanced process. 5.Excellent skills
of communication and teamwork are also expected. 6.Programming experience (Perl/tcl skill) will be
a plus. 7.Experience in advanced process (n16 and beyond) will be a plus. 立即申请
DRC/LVS开发工程师-南京查看详情收起详情
公司/部门: 台积电(南京)
学历要求: 硕士
招聘人数: 若干
岗位介绍:
职责范围: 1.Work closely with process RD team to develop DRC/LVS for design readiness. 2.Provide
customer support to world-wide leading design house. 3.Initial more innovation to continue optimize
development efficiency. 4.Work closely with various departments (Physical design/integration/Device
RD/Product/ESD) on their design requirements. 5.Work closely with EDA partner for tool
qualification and methodology enhance. 职位要求: 1.Good knowledge of semiconductor FEOL/BEOL
process and chip design concepts. Solid understanding of device physics, Layout design is a
plus. 2.Knowledge of EDA partner (Mentor, Synopsys, Cadence, etc.) tools suite is a plus.
Especially Laker /Virtuoso /Calibre. 3.Scripting and programming experience using several of the
following: Perl, Python, C, C++, TCL, Skill. 4.Ability to work across teams to drive a solution,
problem solver and self-motivated. 5.The ideal candidate will have experience in DRC/LVS
development. 6.MS or above in EE, CS related fields. 立即申请